Chief Technology Officer, Vice President, Technology Specialist, Senior Director and Architect

Co-Founded the Digital Health Startup and Served as Chief Technology Officer•	Co-invented the core technology (4 patents issued) for a disruptive consumer product that acquires bio-signals, classifies/predicts mental states, and delivers corresponding stimuli as “training wheels” to guide novice and intermediate meditators to the “mindful state”•	Established the company, developed the corporate strategy, built the advisory board with psychiatrists & neuroscientists teaching at Harvard Medical School and UC Davis, and instituted clinical trials by collaborating with a University of Toronto teaching hospital•	Built and directed a global team of data scientists to develop & integrate emerging technologies including Machine Learning (ML), human-computer interaction / interface (BCI), Internet of Things (IoT) and open-source software;   Led the product development, and successfully classified brainwaves from In-Ear EEG prototypes
    
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AlayaTec, Inc.

•	Defined minimum viable product (MVP) requirements, provided product vision, specified value proposition and market size based on Lean Startup Method and primary/secondary studies, and gained traction with venture capitalists (VC) with quantitative analyses


* Delivered special designs per customer's request.* Built China Design Center.* Acted as a liaison to APAC FAEs and customers to HQ.* Enabled semiconductor companies to rapidly and cost effectively innovate, differentiate and win in their markets.* Combined hardware innovation with software tools and customer support to provide high-value programmable solutions to customers worldwide.* Built and led a global team of highly skilled managers and flexible engineers to innovate, execute and deliver on time with high quality.* Oversaw definitions, micro-architectures, logic designs, system simulations and documentation for DSP IP’s, to create IP databases ready for integration.* Performed all aspects of IP definition-to-delivery flow, from micro-architecture to RTL coding, verifications, logic synthesis, physical layout (place and route), performance (timing), power and area (PPA) closures and documentation.* Established operation infrastructures, conducted experimental tests, evaluated results, to select between alternative micro-architectures and/or implementations, for superior PPA results.
    
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About us

  Tensilica was acquired by Cadence Design Systems, Inc., in 2013. Cadence is actively investing in the innovative Tensilica processor architecture, as well as hiring new engineers and marketing people. Please see www.cadence.com for more information

Tensilica

Delivered Industry’s 1st Artificial Intelligence (AI) Deep Learning (DL) Digital Signal Processor (DSP)•	Delivered all the world’s #1 licensed DSP’s for successful ADAS, 5G mobile, VR, AR & XR visualizations, entertainment, radar, edge AI or other edge computing accelerations•	Mapped software algorithms to hardware, specified Scalar and Single Instruction-Multiple Data (SIMD) Vector Floating-Point (FP, VFP) Instruction Set Architecture (ISA), micro-architected, implemented and benchmarked RTL which takes only 10-15% DSP area and achieving the same MAC/cycle with 15-30% lower power compared to fixed-point to further the company’s leadership•	Authored publications and reviewed presentations for Linley Processor Conference•	Built the DSP design team with ~10 engineers in Silicon Valley and India for Tensilica® (acquired by Cadence® in 2013), and controlled schedule and resources•	Developed and promoted high-performing individuals to create an energetic environment and to grow productivity•	Worked with strategic customers on IP requirements, supervised transfer of completed products, and supported for production•	Resolved a difficult analog/digital bug and saved the company’s only Mobile World Congress (MWC™) demonstration
    
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About us

  Cadence is a leading provider of EDA and semiconductor IP. Our custom/analog tools help engineers design the transistors, standard cells, and IP blocks that make up SoCs. Our digital tools automate the design and verification of giga-scale, giga-hertz SoCs at the latest semiconductor processing nodes. Our IC packaging and PCB tools permit the design of complete boards and subsystems. 

Cadence also offers a growing portfolio of design IP and verification IP for memories, interface protocols, analog/mixed-signal components, and specialized processors. And reaching up to the systems level, Cadence offers an integrated suite of hardware/software co-development platforms. In short, Cadence® technology helps customers build great products that connect the world.


      Cadence Design Systems
  

(now part of Microchip Technology)•	Earned 18th Annual EDN Innovation Award and Portable Design Editor’s Choice with All-in-OneMemory.  Managed entire product life cycles of All-in-OneMemory, by prioritizing according to customer requirements, market trends, company strategy, and resources.•	Managed multiple concurrent cross-functional projects through carefully establishing, tracking and resolving project costs/schedules/resources/risks;  Secure commitments from Software/Technology/Engineering Services/Publications/Marketing/Operation;  Fostered strong cooperation with internal and external resources;  Mitigated risks and unanticipated events.•	Delivered first-pass silicon success without any logic or timing flaws, using in-depth spec-to-testing experience and lessons learned from prior projects, and through carefully selecting and enforcing design/verification/synthesis/DFT/layout/STA practices, inserting new technologies and tools, conducting design audits, and resolved characterization and production issues.•	Directed low-power secure embedded NAND-based memory subsystem developments, through defining design scopes, developing architecture, trading off between various analog IP cores, selecting vendors, assigning development tasks, reviewing VLSI micro-architecture proposals/specs/coding, auditing RTL implementation, and managing prototype bring-up.•	Led debug engineering hands-on.   Perform analytical problem solving, to quickly identify excessive IR drop, and to increase yield by using power-aware scans.  Set day-to-day debug direction and drove resolutions according to project priorities.  Acted as an engineer during emergency.•	Aligned engineering team through hands-on leadership, to produce best works on multiple parallel projects, through recruiting, training, mentoring, coaching, workload balancing, setting group and individual goals, and managing performance.  Managed across geographically dispersed cross-functional teams and offshore resources.
    
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About us

  Silicon Storage Technology, Inc. (SST) is a leading provider of embedded flash and OTP technology. SST develops, designs, licenses, and markets a diversified range of proprietary and patented SuperFlash® and SMARTBIT® memory technology solutions for consumer, industrial and automotive markets. SST was founded in 1989. SST went public in 1995 (NASDAQ: SSTI), and it was acquired by Microchip Technology in April, 2010. SST is now a wholly owned subsidiary of Microchip and it is headquartered in San Jose, California.
 
SST Highlights
#1 embedded flash market share in the Microcontroller market
#1 embedded flash market share in the Smartcard market
More than 75 billion devices shipped worldwide
In volume production from 500nm to 45nm across multiple foundries and IDMs
More than 40 successful technology installations worldwide

•	Supported Design IP by working effectively with customers, CAD tool vendors, Sales and Marketing, to ensure delivery of USB and other mixed signal IP.  Managed across geographically dispersed cross-functional teams to guarantee signal integrity at design, layout, package, board and testing stages.  Prepared and participated in weekly customer meetings.  Presented program status to senior managements of both sides.  Created technical documents and managed technical releases.•	Productized multiple RTL hand-off projects through directing design and support resources abroad and in-house, as well as scheduling, prioritizing, coordinating and supervising engineering tasks.  Completed implementation from synthesis thru post-layout verification and tapeout.  Optimized synthesis scripts to maximize design performance.  Ran static timing analysis (STA) to verify post-layout convergence.•	Retained key customer through patiently and diligently resolving communication and technical issues, and proactively identified critical testability and manufacturability problem to avert re-spin for customer.
    
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About us

  Faraday Technology Corporation (TWSE: 3035) is a leading ASIC design service and IP provider, certificated to ISO 9001 and ISO 26262. The broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDR2/3/4, low-power DDR1/2/3, MIPI, V-by-One, USB 2.0/3.1 Gen 1, 10/100/1000 Ethernet, Serial ATA, PCI Express, and programmable SerDes, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China.

Faraday Tech

•	Consulted and educated professional investors on industry trends and latest technologies, products and services.  Clients include Bear Stearns, Fidelity and others.


About us

  GLG (Gerson Lehrman Group, Inc.) is the world’s leading platform for professional learning. Business leaders, investors, consultants, social entrepreneurs, and other top professionals rely on GLG to learn in short- and long-term engagements from a membership of more than 500,000 experts. Clients partner with GLG to address their most complex strategic challenges, make better business decisions, and advance their careers through conversations, mentorships, small group convenings, surveys, and other interactions—all within a rigorous compliance framework. Global, technology-driven, and nimble, GLG’s approximately 1,400 employees work in 22 offices in 12 countries.


      GLG
        
  

•	Productized (FCS) three releases of VLSI for $14 million program on original schedules.  The chip is the core engine inside Nortel secured VPN product line OPTera Metro 1200, 1400 and 1450.  The OPTera Metro family has been deployed by AT&amp;T, KPN among others.•	Performed scheduling and reviews.  Determined and drove new design/verification methodology and digital architecture.  Created and executed detailed development and test plans.•	Mitigated risks of complex FPGA / ASIC projects by utilizing strong technical expertise to anticipate unplanned challenges, to develop mitigation plans, and to remove difficult obstacles within the team and cross-functionally in multiple product developments.•	Accelerated development speed by approximately 20% by evaluating, defining, integrating and standardizing new high speed front-end digital design processes, EDA tools, design rules and verification methodology to handle 32,000 lines of RTL codes or 2 M gates.•	Rescued $1.8 million revenue and saved key customer.  Averted product returns by quickly isolating elusive system-level fault and implementing urgent patch solution.
    
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About us

  Nortel was a recognized leader in delivering communications capabilities that make the promise of Business Made Simple a reality.  Nortel developed next-generation technologies, for both service provider and enterprise networks, to support multimedia and business-critical applications. Nortel's technologies were designed to help eliminate today's barriers to efficiency, speed and performance by simplifying networks and connecting people to the information they need, when they need it.  At its peak, Nortel did business in more than 150 countries around the world.


      Nortel
  

•	Managed and led system-on-chip (SOC) engineering.  Evaluated, selected and coordinated offshore foundry, contract manufacturers, test and assembly house, and ASIC back-end vendor.  Interfaced with internal mechanical, electrical, and firmware developers.•	Specified, architected, developed and verified mixed-signal standard-cell SOC ASIC.  Designed reusable IP cores.  Performed Verilog HDL integrations, simulations, verifications and syntheses.  Supervised clock tree synthesis (CTS) and layout.  Conducted pre- and post- layout static timing analysis (STA) and optimization.  Closed full-chip SDF timing issues.
    
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•	Revitalized 733 MHz 4MB level-3 (L3) cache snooper on 25-million-transistor CPU by re-microarchitecting fully-pipelined FSM to hide memory latency, and to incorporate ECC.•	Saved over 12 man-months of effort by reestablishing timing environment modules for BUS cluster on Intel Architecture 64 bits (IA-64) superscalar Itanium® full-custom .18 micron microprocessor.•	Ensured meeting chip operating frequency goals by testing and certifying Synopsys® synthesis scripts for use by over 100 logic designers.•	Debugged Pentium MMX IA32 microprocessor using component debug testers, through cross-site/cross-division engagements.
    
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About us

  At Intel, building a better world is our business. Our mission is to utilize the power of Moore's Law to bring smart, connected devices to every person on earth while serving as a role model for how companies should operate.

We power amazing experiences through a diverse product line and exciting partnerships. Our strategy is a virtuous cycle of innovation—the cloud and the data center, the Internet of Things, memory and FPGAs all bound together by the goal of greater connectivity and enhanced performance. 

Our global team, over 107,000 strong across 58 countries, is a powerhouse of engineering and technological excellence that empowers solutions to the world's toughest problems while creating the technology of tomorrow. 

We are Intel, and Amazing Works Here.


      Intel Corporation
        
  

Located 40 miles south of San Francisco in California’s Silicon Valley, Santa Clara University offers rigorous undergraduate curricula in the arts and sciences, business, and engineering. It has nationally recognized graduate and professional schools in business, law, engineering, pastoral ministries, counseling psychology, education, and theology.

Founded in 1851 by the Society of Jesus as “Santa Clara College,” SCU is California’s oldest operating institution of higher learning. It was established on the site of Mission Santa Clara de Asís, the eighth of 21 California missions. The 8,800-student university draws upon more than 450 years of the Jesuit tradition of educating the whole person for service and leadership.

Santa Clara University is a Jesuit, Catholic university that educates citizens and leaders to build a more just, humane, and sustainable world. In addition to abundant career opportunities provided by our ideal location, students have access to a variety of educational, cultural, and recreational activities. The 106-acre campus features beautiful gardens and landscaping, and has more than 51 buildings, including 10 residence halls, two libraries, a student center, and extensive athletic facilities.

The 2013 edition of U.S. News & World Report’s “Best Colleges” ranked SCU among master’s universities:

• No. 2 comprehensive university in the West
• Highest average freshman retention rate (93%) in the West
• Highest average graduation rate (86%) in the West
• No. 14 undergraduate engineering program in the U.S.

Named as one of the nation’s top 75 institutions for undergraduate education by Forbes magazine’s “List of America’s Top Colleges,” SCU was also listed as one of the top 50 in the nation for the best value among private universities in Kiplinger’s Personal Finance magazine. The undergraduate business program is No. 35 in the nation, according to “The Best Undergraduate B-schools,” by Bloomberg Businessweek magazine.

Chief Technology Officer at AlayaTec, Inc.

AlayaTec, Inc.

Chief Technology Officer

AlayaTec, Inc.

Chief Executive Officer

Tensilica

Consulting Services Manager

Cadence Design Systems

Sr. Design Engineering Manager

SST

Manager, Design Engineering

Faraday Tech

Technology Manager

GLG

Technology Advisor

Nortel

Principal Engineer

ACQIS

Lead Engineer

Intel Corporation

Senior Design Engineer

Santa Clara University

CS

BS

Santa Clara University

Computer Engineering

MS (coursework)